Analog-to-digital converter

ABSTRACT

One or more embodiments of a successive approximation type analog-to-digital converter that converts an analog input into a digital conversion value and outputs the digital conversion value, may include: a capacitance DAC that generates a bit-by-bit potential based on an analog input; a comparator that compares the potential generated by the capacitance DAC, wherein the comparator is a memory cell rewriting type, the comparator includes a first stage current mirror type operational amplifier; and a second stage memory cell; a conversion data generator that generates conversion data of resolution bits based on a comparison result of the comparator; and a correction circuit that corrects an output error of the conversion data caused by an offset error of the comparator by adding or subtracting an offset correction value that is a fixed value, and outputs the conversion data as a digital conversion value.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a continuation application of InternationalApplication No. PCT/JP2020/041990, filed on Nov. 11, 2020, the entirecontents of which are incorporated herein by reference.

BACKGROUND

The disclosure relates to an analog-to-digital converter (hereinafterreferred to as an A/D converter), and in particular, to a successiveapproximation type A/D converter.

An A/D converter is a device that converts an input analog “voltage”into a numerical value for the purpose of digital processing, and asuccessive approximation type is often used because of its good balanceof high-speed performance, area, and power consumption.

A successive approximation type A/D converter compares potentialsgenerated by a capacitance DAC based on analog input potentials with acomparator, feeds back the results of the comparison to a conversiondata generator, and conveys the approximate data candidates to thecapacitance DAC. This repetition is repeated for resolution bits (nbits: n times) to obtain digital conversion values.

A comparator is a circuit with a large current consumption in an A/Dconverter, and a memory cell rewriting type is used which has a smallcurrent consumption and high speed (see for example, Patent PublicationNo. JPH05-346441A (Patent Document 1) and Patent Publication No.JP2010-109937A (Patent Document 2)). As illustrated in FIG. 4, a memorycell rewriting type comparator includes a first stage current mirrortype operational amplifier 10 and a second stage memory cell 20, whereinthe output of the operational amplifier 10 is connected to “L” and “R”of the memory cell 20. A slight difference in the potentials of “L” and“R” at the instant when the memory cell 20 is turned on by a clockdetermines the 0/1 of the memory cell 20.

However, a memory cell rewrite type comparators has a large offseterror. For this reason, related technologies for avoiding or reducingthe offset error are disclosed.

One technology is to increase the gate width of the elements thatcomprise a comparator. For example, for the gate width of the MOStransistor in the first stage operational amplifier 10, the offset errorbecomes small in inverse proportion to the 1/square of the gate width.

However, when the gate width is increased, the current is inverselyproportionally reduced and the gate capacitance is proportionallyincreased, so that the gate length must be increased to obtain the samespeed, which increases the layout area and also increases the currentconsumption.

In a memory cell rewriting type comparator, the difference in parasiticcapacitance due to wiring of the “L” and “R” nodes also produces anoffset error. There is a method of offset correction by adding achangeable capacitance to the “L” and “R” nodes to take advantage of theabove-mentioned effect. However, this method requires incorporatedmultiple structures of capacitive elements with switches, each of whichis a huge mechanism in terms of layout, resulting in an increase in thelayout area.

Thus, if a circuit is designed to have a small offset error, the circuitcomprises a large layout area and a large current consumption. Inaddition, if a circuit for correcting an offset error is added to ananalog circuit, it results in adding a circuit with a larger layout areathan that of the comparator circuit.

SUMMARY

One or more embodiments of a successive approximation typeanalog-to-digital converter that converts an analog input into a digitalconversion value and outputs the digital conversion value, may include:a capacitance DAC that generates a bit-by-bit potential based on ananalog input; a comparator that compares the potential generated by thecapacitance DAC, wherein the comparator is a memory cell rewriting type,the comparator includes a first stage current mirror type operationalamplifier; and a second stage memory cell; a conversion data generatorthat generates conversion data of resolution bits based on a comparisonresult of the comparator; and a correction circuit that corrects anoutput error of the conversion data caused by an offset error of thecomparator by adding or subtracting an offset correction value that is afixed value, and outputs the conversion data as a digital conversionvalue.

One or more embodiments of a method of setting an output of a successiveapproximation type analog-to-digital converter comprising a capacitanceDAC that generates a bit-by-bit potential based on an analog input, acomparator that compares potentials generated by the capacitance DAC,and a conversion data generator that generates conversion data of aresolution bit based on a comparison result of the comparator, mayinclude: storing an output error of the conversion data as an offsetcorrection value in a non-volatile memory, the output error of theconversion data being caused by an offset error of a memory cellrewriting type comparator comprising a first stage current mirror typeoperational amplifier and a second stage memory cell; setting if theoffset correction value stored in the non-volatile memory is stored to aregister; adding or subtracting a value stored in the register to orfrom the conversion data; and outputting the result as a digitalconversion value.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a block diagram illustrating an A/D converter according to oneor more embodiments;

FIG. 2 is a diagram illustrating output errors of a conversion dataoutput from a conversion data generator such as illustrated in FIG. 1;

FIG. 3 is a diagram illustrating output errors of digital conversionvalues corrected by a correction circuit such as illustrated in FIG. 1;and

FIG. 4 is a block diagram illustrating a comparator according to one ormore embodiments.

DETAILED DESCRIPTION

A/D converters according to one or more embodiments are explained belowin accordance with the accompanying drawings.

FIG. 1 is a block diagram illustrating an A/D converter according to oneor more embodiments. An A/D converter 1 is a successive approximationtype and includes a capacitance DAC 2, a comparator 3, a conversion datagenerator 4, and a correction circuit 5.

In the A/D converter 1, potentials generated by the capacitance DAC 2based on analog input potentials are compared by the comparator 3, theresult is fed back to the conversion data generator 4, and theconversion data generator 4 conveys the approximate data candidates tothe capacitance DAC 2. This repetition is repeated for the resolutionbit (n bits: n times), and the conversion data generator 4 outputsconversion data of the resolution bit.

FIG. 4 is a block diagram illustrating a comparator according to one ormore embodiments. This comparator is a memory cell rewriting typeincluding a current mirror type operational amplifier 10 in a firststage and a memory cell 20 in a second stage. The gate width of theelements comprising the comparator 3 may be configured with the minimumgate width of an IC process (e.g., gate width of 0.1 μm) or a gate widthclose thereto (gate width of 0.2 μm or less), and a not small offseterror may be allowed. For example, when the gate width is 0.1 μm, theoffset error is ±60 mV. This is a large output error that corresponds tothe maximum of 206 LSBs (1 LSB is 0.29 mV) in terms of 12-bitresolution.

The correction circuit 5 is a circuit for correcting an output errorcaused by an offset error of the comparator 3 from the conversion dataoutput from the conversion data generator 4, and includes a memory 51, aregister 52, and an adder 53.

The memory 51 may be a non-volatile memory such as a flash memory, andthe output error of the conversion data output from the conversion datagenerator 4 measured in a shipping inspection may be stored as an offsetcorrection value.

The register 52 may be a temporary storage circuit in which an offsetcorrection value read from the memory 51 is stored. It may be configuredto be settable whether or not to store the offset correction value inthe register 52. For example, when the reading of the offset correctionvalue from the memory 51 and the storing of the offset correction valuein the register 52 are performed by a host device operating underprogram control, the user can set whether or not to store the offsetcorrection value in the register 52 by the program. The value of theregister 52 in which the offset correction value is not stored is “0”.

The adder 53 may be a digital adder. The adder 53 digitally adds thevalue stored in the register 52 to the conversion data output from theconversion data generator 4 and outputs the result as a digitalconversion value of the A/D converter 1. Accordingly, when the offsetcorrection value is stored in the register 52, the value obtained bydigitally adding the offset correction value to the conversion dataoutput from the conversion data generator 4 is output as the digitalconversion value of the A/D converter 1, and when the offset correctionvalue is not stored in the register 52, the conversion data output fromthe conversion data generator 4 is output as the digital conversionvalue of the A/D converter 1.

FIG. 2 is a diagram illustrating output errors of the conversion dataoutput from the conversion data generator illustrated in FIG. 1. Morespecifically, FIG. 2 illustrates output errors of the conversion dataoutput from the conversion data generator 4 when the comparator 3 isconfigured with the minimum gate width allowed by the process. Referringto FIG. 2, a large margin of errors about ±120 LSBs is observed. This isdue to variations in element characteristics of individual circuits andwiring parasitic capacitances.

As a result of a close examination of the output errors in FIG. 2, theinventor finds that the output errors are constant regardless of inputpotentials. Moreover, these output errors are constant without beingaffected by temperature. If output errors are constant, or in otherwords, if the margin of output errors is known, the output error of theconversion data output from the conversion data generator 4 is measuredin a shipping inspection, and the measured output error, which isconsidered as the offset correction value, may be corrected by simplyadding or subtracting the offset correction value to the conversion dataoutput from the conversion data generator 4.

FIG. 3 is a diagram illustrating output errors of digital conversionvalues corrected by the correction circuit illustrated in FIG. 1. Morespecifically, FIG. 3 illustrates digital conversion values of the A/Dconverter 1 output from the correction circuit 5. FIG. 3 indicates thatoutput errors of the conversion data output from the conversion datagenerator 4 are corrected and fine results are obtained.

As explained above, one or more embodiments may comprise a capacitanceDAC 2 that generates a bit-by-bit potential based on analog input, acomparator 3 that compares potentials generated by the capacitance DAC2, and a conversion data generator 4 that generates conversion data ofresolution bits based on the comparison result of the comparator 3, andmay be a successive approximation type A/D converter 1 that converts theanalog input into digital conversion values and outputs the digitalconversion values. The comparator 3 may be a memory cell rewriting typecomprising a current mirror type operational amplifier 10 in a firststage and a memory cell 20 in a second stage. The comparator 3 alsocomprises a correction circuit 5 that corrects output errors of theconversion data caused by offset errors of the comparator 3 by adding orsubtracting an offset correction value, which is a fixed value, and thatoutputs corrected conversion data as a digital conversion value.

Since this configuration may correct output errors of the conversiondata by adding or subtracting offset correction values, the offset errorin the memory cell rewriting type comparator 3 may be tolerated, and thehigh-speed A/D converter 1 with small current consumption may beachieved without increasing the layout area or current consumption ofthe comparator 3.

In one or more embodiments, the offset correction value is an outputerror of the conversion data output from the conversion data generator 4measured in a shipping inspection. With this configuration, the offsetcorrection value may be set only by measuring the output error of theconversion data output from the conversion data generator 4 in theshipping inspection.

In one or more embodiments, the correction circuit 5 comprises anon-volatile memory (memory 51) in which offset correction values arestored, a register 52 in which the offset correction values stored inthe memory 51 may be selectively stored, and a digital adder that addsand subtracts the values stored in the register to and from theconversion data (adder 53).

This configuration allows the user to select whether the conversion dataoutput from the conversion data generator 4 is to be offset correctionor not.

For example, when the user wants to treat the digital conversion valueoutput from the A/D converter 1 as a relative value rather than anabsolute value, that is, when ‘the user wants to control “D”, which isthe digital conversion value output from the A/D converter 1, to bebetween “D−10” and “D+10”,’ “offset correction” is not necessary;therefore, the operation of reading the offset correction value from thememory 51 and storing the offset correction value in the register 52 maybe omitted.

On the other hand, when the user wants to treat the A/D conversion valueas an absolute value, that is, when the user wants to control thedigital conversion value “D” obtained by the A/D converter 1′ to be ‘1.0V (“D”=the conversion range of the A/D converter 1 with 3413:12-bit isbetween 0 and 1.2 V),’ the value of the digital conversion value must beabsolute; therefore, the operation of reading the offset correctionvalue from the memory 51 and storing the offset correction value in theregister 52 is necessary to be performed.

In one or more embodiments, the gate width of the elements comprisingthe comparator 3 may be 0.2 μm or less. With this configuration, thelayout area and the current consumption of the comparator 3 may bereduced.

In one or more embodiments, the gate width of the elements comprisingthe comparator 3 may be the minimum gate width of the IC process.

With this configuration, the layout area and current consumption ofcomparator 3 may be reduced.

An A/D converter according to one or more embodiments may eliminateoffset errors without increasing the layout area or current consumption,even if a A/D converter includes a memory cell rewriting typecomparator.

An A/D converter according to one or more embodiments may accept theoffset error in a memory cell rewriting type comparator since the outputerror of the conversion data may be corrected by adding and subtractingoffset correction values. Therefore, an A/D converter according to oneor more embodiments may provide an A/D converter with a small currentconsumption without increasing the layout area and current consumptionof a comparator.

The present invention may not be limited to the above-describedembodiments, and that each embodiment may be changed as appropriatewithin the scope of the technical concept of the present invention. Thenumber, position, shape, etc. of the above-described components may notbe limited to the above-described embodiments, and may be made into anumber, position, shape, etc. suitable for implementing the presentinvention. The same sign is assigned to the same component in eachfigure.

1. A successive approximation type analog-to-digital converter thatconverts an analog input into a digital conversion value and outputs thedigital conversion value, comprising: a capacitance DAC that generates abit-by-bit potential based on an analog input; a comparator thatcompares the potential generated by the capacitance DAC, wherein thecomparator is a memory cell rewriting type, the comparator comprises: afirst stage current mirror type operational amplifier; and a secondstage memory cell; a conversion data generator that generates conversiondata of resolution bits based on a comparison result of the comparator;and a correction circuit that corrects an output error of the conversiondata caused by an offset error of the comparator by adding orsubtracting an offset correction value that is a fixed value, andoutputs the conversion data as a digital conversion value.
 2. Theanalog-to-digital converter according to claim 1, wherein the offsetcorrection value comprises an output error of the conversion data outputfrom the conversion data generator measured in a shipping inspection. 3.The analog-to-digital converter according to claim 1, wherein thecorrection circuit comprises a non-volatile memory in which the offsetcorrection value is stored; a register that is capable of selectivelystoring the offset correction value stored in the non-volatile memory;and a digital adder that adds and subtracts values stored in theregister to and from the conversion data.
 4. The analog-to-digitalconverter according to claim 2, wherein the correction circuit comprisesa non-volatile memory in which the offset correction value is stored; aregister that is capable of selectively storing the offset correctionvalue stored in the non-volatile memory; and a digital adder that addsand subtracts values stored in the register to and from the conversiondata.
 5. The analog-to-digital converter according to claim 1, wherein agate width of elements comprising the comparator is 0.2 μm or less. 6.The analog-to-digital converter according to claim 2, wherein a gatewidth of elements comprising the comparator is 0.2 μm or less.
 7. Theanalog-to-digital converter according to claim 3, wherein a gate widthof elements comprising the comparator is 0.2 μm or less.
 8. Theanalog-to-digital converter according to claim 1, wherein a gate widthof elements comprising the comparator is the minimum gate width of an ICprocess.
 9. The analog-to-digital converter according to claim 2,wherein a gate width of elements comprising the comparator is theminimum gate width of an IC process.
 10. The analog-to-digital converteraccording to claim 3, wherein a gate width of elements comprising thecomparator is the minimum gate width of an IC process.
 11. A method ofsetting an output of a successive approximation type analog-to-digitalconverter comprising a capacitance DAC that generates a bit-by-bitpotential based on an analog input, a comparator that comparespotentials generated by the capacitance DAC, and a conversion datagenerator that generates conversion data of a resolution bit based on acomparison result of the comparator, comprising storing an output errorof the conversion data as an offset correction value in a non-volatilememory, the output error of the conversion data being caused by anoffset error of a memory cell rewriting type comparator comprising afirst stage current mirror type operational amplifier and a second stagememory cell; setting if the offset correction value stored in thenon-volatile memory is stored to a register; adding or subtracting avalue stored in the register to or from the conversion data; andoutputting the result as a digital conversion value.